Building an Application-specific Memory Hierarchy on FPGAs
نویسندگان
چکیده
The high potential performance of FPGAs cannot be exploited if a design suffers a memory bottleneck. Therefore, a memory hierarchy is needed to reuse data in on-chip memories and minimize the number of accesses to off-chip memory. Buffer memories not only hide the external memory latency, but can also be used to remap data and augment the on-chip bandwidth through parallel access of multiple buffers. This paper presents a step-by-step methodology to construct such a memory hierarchy. Special care is taken of the reusability of design modules and the optimization of address expressions to improve the performance.
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